specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 61009 ms 20061207-s00003 no.a1499-1/7 LV56081GP overview the LV56081GP is charge pump power supply for ccd. functions ? the charge pump boosts the +3.3v input by multiplying with +6, then by -3 to regulate the voltage to the specified level. ? the output voltage is +15v, -5.5v necessary for ccd. ? soft start function incorporated, which reduces the inrush current at start of charge pump. ? short-circuit protection function incorporated. ? four types of operatin g frequency selectable. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v dd max 3.5 v allowable power dissipation pd max with specified substrate *1 0.8 w operating temperature topr -20 to +80 c storage temperature tstg -40 to +125 c *1 : specified substrate : 40mm 50mm 0.8mm, glass epoxy board allowable operating ratings at ta = 25 c, pgnd = 0v ratings parameter symbol conditions min typ max unit supply voltage v dd 3.0 3.3 3.45 v input clk frequency ckin sel=h *2 0.1 8 mhz input high voltage v in h en pin 0.7v dd v dd v input low voltage v in l en pin -0.1 0.4 v *2 : note that the charge pump frequency should be adjus ted with s0/s1 so that it becomes 2mhz or less. bi-cmos lsi for ccd charge pump power supply orderin g numbe r : ena1499
LV56081GP no.a1499-2/7 electrical characteristics at ta = 25c, v dd = 3.3v, sgnd = 0v, pgnd = 0v,ih=20ma, il=5ma, s0=h, s1=l, unless otherwise specified ratings parameter symbol conditions min typ max unit i dd 1 en = l 15 30 a circuit current dissipation i dd 2 en = h no load 17 25 ma vh output load current ih ave v dd = 3.0v 20 ma vl output load current il ave v dd = 3.0v -8 ma v dd = 3.0 to 3.45v, design guarantee 1.305 v reference voltage vref ta = -20c to +80c, design guarantee 1.239 1.37 v vh 14.55 15 15.35 v output voltage accuracy vl -5.65 -5.5 -5.25 v output voltage at off voff after capacitive discharge -50 0 +50 mv vh holding time toff vloff vhoff 5 ms protection circuit masking time tmask 18 ms vh load regulation ? vh load 1ma 20ma 30 mv vl load regulation ? vl load 0.5ma 8ma 50 mv input pin current iin pins en, s0, s1, sel and clk 12.6 17.5 22.5 a vh monitoring voltage vtvlon 8 v power efficiency peff cp+regulator (vh+vl) 70 % inrush current irush 600 ma oscillation frequency f clk 1.5 2 2.5 mhz note : the design specification items are design guarantees and are not measured. package dimensions unit : mm (typ) 3322a sanyo : vct24(3.5x3.5) 3.5 3.5 0.4 0.8 (0.035) 1 2 24 0.5 (0.5) top view side view side view bottom view (0.125) (c0.17) (0.13) 0.25 -20 0 20 40 60 80 100 0 1.0 0.8 0.6 0.4 0.2 pd max -- ta 0.36 ambient temperature, ta -- c allowable power dissipation, pd max -- w specified board: 40 50 0.8mm 3 glass epoxy board.
LV56081GP no.a1499-3/7 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 24 23 22 21 20 19 s0 s1 en sgnd sv dd clk sel vh c23 vh c22 c21a nc c11b pgnd c12b pv dd c11a c12a vm c13 c31b pgnd1 c31a vl c32 vl c33 test top view pin function pin no. name mode 1 s0 charge pump frequency changeover pin 2 s1 charge pump frequency changeover pin 3 en system enable pin (hi active) 4 sgnd small signal system gnd pin 5 sv dd small signal system v dd pin 6 clk external clk input pin 7 sel clk selector pin (l: built-in clk, h: external clk) 8 vh c23 vh (+15v) regulator output pin 9 vh c22 boost voltage output (+6v dd ) 10 c21a boost capacitor connection pin (on the load transfer side) 11 nc 12 c11b boost capacitor co nnection pin (driver side) 13 pgnd +3-fold boost power gnd pin 14 c12b boost capacitor co nnection pin (driver side) 15 pv dd power system v dd pin 16 c11a boost capacitor connecti on pin (load transfer side) 17 c12a boost capacitor connecti on pin (load transfer side) 18 vm c13 boost voltage output (+3v dd ) 19 c31b +2-fold and -1-fold boost capacitor connection pin (driver side) 20 pgnd1 +2-fold and -1-fold boost power gnd pin 21 c31a -1-fold boost capacitor connection pin (load transfer side) 22 vl c32 boost voltage output (-3v dd ) 23 vl c33 vl (-5.5v) regulator output pin 24 test test pin (open or gnd short-circuited)
LV56081GP no.a1499-4/7 block diagram 15 13 14 12 16 17 18 10 9 8 1 2 7 6 5 4 20 19 21 22 23 3 24 vl c32 c31a c31b pgnd1 pgnd sv dd pv dd v dd 3.3v 1 f /3v dd 0.22 f /3v dd 1 f /v dd 2.2 f /3v dd 1 f /v dd 1 f /2v dd 2.2 f /6v dd 2.2 f 1 f /3v dd 10 f /v dd 1 f vl=-7.5v vl c33 en test pgnd c12b c11b c11a c12a vm c13 c21a vh c22 +6v dd +3v dd -3v dd s0 s1 sel clk lo : internal clk hi : external clk vh c23 vh=+15v a to a +3 times step up circuit +2 times step up circuit -1 times step up circuit bandgap voltage reference tsd sequence generator timing generator vh reg 2bitmux 2mhz oscillator vl reg divider mux
LV56081GP no.a1499-5/7 short-circuit protection vh and vl output pins incorporate the short-circuit protection function. when the output pins are short-circuited to allow the large current to flow, ic is latched off to interrupt output. to reset from the interrupted state, set the en pin to l, then reset it again to h. frequency selection the charge pump operating frequency can be changed with s0 and s1 logics. for light load, the reactive load can be reduced by lowering the operating frequency. sel logic also enables synchronou s operation with external clk. the charge pump is operated with the frequency equivalent to 1/2 of input clk. (the ic internal oscillator is used for the sequence, so that it is normally on regardless of sel. for minimum 9.4ms after startup with the en signal set to h, the ic internal clock is used to operate th e charge pump with 1 mhz regardless of the input of sel, s0, and s1 pins. after the 9.4ms(min) period, the charge pump frequency is changed ov er according to the state of sel, s0, and s1 pins. the changeover frequency is set as shown in the table right. internal equivalent circuit dq q a b sel dq q dq q dq q clk/8 clk/4 clk/2 clk y y s1 s0 sel l h a b y s0 l h s1 y clk clk/2 l l l h h h clk/4 clk/8 s0 pin s1 pin sel pin clk pin internal 1mhz vh regulator start signal l ? h in 9.4ms (min) after en = h external signal input pin internal signal truth table 2-input multiplexer 4-input multiplexer truth table charge pump clock cp operating frequency s0 s1 sel=l sel=h l l 1mhz 1/2 clk h l 500khz 1/4 clk l h 250khz 1/8 clk h h 125khz 1/16 clk sel l ic internal oscillator h synchronous operation with external clk
LV56081GP no.a1499-6/7 external clock signal startup sequence v dd en s0 s1 sel clk charge pump (c23) regulator (c23) sel=h (external clock) do not attempt change the signal after 9.4ms from en = h do not attempt change the signal after 9.4ms from en = h do not attempt change the signal after 9.4ms from en = h set en = h by setting v dd at 3v or more stop at en = l or over-current protection never set v dd at 3v or less till the sequence is over (7.5ms after en = l). frequency selection frequency selection external clock selected do not attempt change the signal after 9.4ms from en = h do not attempt change the signal after 9.4ms from en = h do not attempt change the signal after 9.4ms from en = h frequency selection frequency selection external clock selected frequency selection frequency selection external clock selected * internal 1mhz sel=l (internal clock) * cp clock 1mhz * cp clock 500khz * cp clock 250khz * cp clock 125khz * cp clock 1/2 * cp clock 1/4 * cp clock 1/8 * cp clock 1/16 * ic internal signal internal clock start at 1mhz 9.4ms (min) internal clock start at 1mhz 9.4ms (min) steady operation stop sequence 7.5ms (max) steady operation stop sequence 7.5ms (max) en pin and v dd though the sequence operation is made at startup, startup is not effectuated if the internal circuit has not been reset. to reset the internal circuit, it is necessary to keep the en pin at l till v dd becomes 3v or more. note that operation with v dd and en pin short-circuited cannot be made. since the sequence operation is incorporated for stop of operation, the charge pump remains active till 7.5ms (max) passes after setting the en pin to l. during this period, v dd must be kept at 3v or more to allow the internal sequence logic to operate correctly.
LV56081GP ps no.a1499-7/7 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. rise/fall sequence +6v dd +3v dd -3v dd vh vl en i dd vref 600ma max 5.5ms 2ms 2ms 3.3ms vtvlon to ff 18.9ms 6.1ms * reg output charge pump output *the vl startup time at vh 10v and after elapse of 6.1ms is t he reference time for clk = 2mhz. this catalog provides information as of june, 2009. specifications and information herein are subject to change without notice.
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